1. Field
Exemplary embodiments of the present invention relate to a semiconductor integrated circuit design, and more particularly, to a semiconductor integrated circuit having a differential signal transmission structure and a method for driving the same.
2. Description of the Related Art
In general, a signal transmission line used in a semiconductor integrated circuit is referred to as a bus. The bus may be divided into a single-ended type using one line and a differential type using two lines. The differential type bus has an advantage in that it has small current consumption because the signal swing thereof is smaller than that of the single-ended type bus.
Meanwhile, a semiconductor integrated circuit typically uses a hierarchical bus structure. For example, a memory device such as a DRAM uses a hierarchical bus structure divided into a global data bus, a local data bus, and a segment data bus, in order to transmit data between a memory cell and an input/output interface. Among the buses, the global data bus is implemented with a single-ended type bus, and the local data bus and the segment data bus are implemented with a differential type bus.
FIG. 1 is a block diagram illustrating a data read path of a conventional DRAM.
Referring to FIG. 1, the data read path of the conventional
DRAM includes a memory cell 100, a bit line sense amplifier (BLSA) 120, a local sense amplifier (LSA) 140, and a global sense amplifier (IOSA) 160. The BLSA 120 is configured to sense and amplify data of the memory cell 100, loaded on a bit line pair BL and BLB. The LSA 140 is configured to sense and amplify an output signal of the BLSA 120, loaded on a segment data line pair SIO and SIOB, in response to an LSA enable signal LSA_EN. The IOSA 160 is configured to sense and amplify an output signal of the LSA 140, loaded on a local data line pair LIO and LIOB, and transmit the amplified signal to a global data line GIO.
Here, the LSA 140 amplifies the data loaded on the segment data line pair SIO and SIOB and transmits the amplified data to the local data line pair LIO and LIOB, during a read operation of the DRAM.
With the increase in a degree of integration of a DRAM, loading on the local data line pair LIO and LIOB may increase, thus reducing a voltage difference between the local data line pair LIO and LIOB. Since a sensing margin of the IOSA 160 is increased by the amplification operation of the LSA 140, it is possible to advance a point of time at which the IOSA 160 is driven.
However, since the employment of the LSA 140 increases a swing width of the local data line pair LIO and LIOB having a large load, the current consumption inevitably increases.
FIG. 2 is a waveform diagram illustrating the LSA enable signal LSA_EN and voltage levels on the data line pair LIO and LIOB over time in the conventional DRAM.
The operation of the LSA 140 is controlled by the LSA enable signal LSA_EN. When the LSA enable signal LSA_EN is activated to a logic high level, the LSA 140 is enabled to develop the local data line pair LIO and LIOB precharged with a core voltage level VCORE.
Typically, an enable period of the LSA 140 is set based on a voltage difference on the local data line pair LIO and LIOB when a PVT (process, voltage, and temperature) condition is the worst. Therefore, when the PVT condition is favorable, the swing width of the local data line pair LIO and LIOB may dramatically increase, and thus effecting a precharge current as well as a sensing current. Furthermore, when the swing width of the local data line pair LIO and LIOB increases, a precharge time for the local data line pair LIO and LIOB increases, resulting in the degradation of an operation speed.